Improving Instruction-Level Parallelism by Exploiting Global Value Locality

Several studies have pointed out that the values produced by the execution of a program’s instructions are often quite repetitive. There are basically two approaches that have been proposed for exploiting this value locality – 1) reusing the results of a prior execution of an instruction, and 2) predicting the value that will be produced by the current execution of an instruction based on the previous values it has produced. Existing value reuse and prediction schemes operate at the level of a single instruction or short sequence of instructions so that the caches used to temporarily store previous values are typically indexed using the instruction addresses. However, we have found that different instructions often produce the same values. We introduce the Speculative Value Cache (SVC) to globally exploit values previously produced by any instructions by indexing this cache with a hash function of the values of the instruction’s input operands rather than indexing with the instruction address. With this approach, the current instruction can directly use the result value found in the speculative value cache even if it has been previously produced by a different instruction. We partition the SVC into several different sections based on the instruction category, such as arithmetic, shift, or load, for instance, since different types of instructions will produce different output results when given the same input operands. Our simulation results based on the SimpleScalar simulator show that embedding the SVC in a realistic 4-issue superscalar processor could improve the performance of the SPEC95 integer benchmarks by as much as 25%. Increasing the issue-with allows this mechanism to achieve even higher performance with an 8-issue processor having speedups of 5-42% and a 16-issue processor producing speedups of up to 50%. We also demonstrate the sensitivity of these results to changes in important design parameters.